As input/output (I/O) interface speeds increase, I/O circuitry becomes more sensitive to the effects of parasitic inductances. Such parasitic inductances can result from sources such as bond wires, IC package leads, external supply lines that provide operating power, etc. The problem with parasitic inductances is that they cause very high supply line impedances to develop at the resonance frequency of a particular circuit. This may lead to circuit oscillation 10 as is shown in FIG. 1. Such I/O power supply oscillations degrade the timing and reliability of an I/O interface. In order to avoid such undesirable effects on I/O operation and function, parasitic inductances must be suitably compensated for and/or controlled.
One typical method of controlling parasitic inductance involves connecting a capacitor between power supply leads. Such a connection provides a passive bypass that decreases supply line oscillations resulting from external inductances. However, such a connection does not significantly reduce supply line oscillations caused by internal inductances. To this end, another typical method involves connecting an on-chip capacitor between the internal power supply leads. In such an arrangement, the capacitor acts as a bypass in the same manner as the capacitor connected externally. The resulting non-oscillating circuit performance 20 is shown in FIG. 2. However, in order to be effective, the internal capacitor must be very large. This has the drawback of occupying a significant portion of the chip area. Consequently, this method is generally undesirable when minimization of die area is of concern.
Another prior art approach involves increasing the amount of charge stored or delivered to a given amount of added on-chip capacitance by actively increasing the voltage variation across the terminals of such a capacitance. FIG. 3 shows an I/O interface 30 that uses this technique. The I/O interface 30 includes mutually exclusive switches that configure capacitors 32 and 34 to either be in a charging phase (configured as a shunt across I/O VDD 36 and I/O VSS 38) or in a discharging phase (configured in serried with I/O VDD 36 and I/O VSS 38). The I/O interface 30 has two stages: an average voltage potential (Vave) tracking stage 40 and an instantaneous voltage potential (Vinst) tracking stage 42. The mutually exclusive switches are driven by drivers 44 and 46. Each driver 44 and 46 provides two outputs with enough voltage offset to ensure minimal leakage through both charge and discharging switches during switching activity.
Instantaneous voltage supply variation is monitored by coupling I/O VDD 36 and I/O VSS 38 onto inputs of driver 46, where driver 46 is dynamically biased about the average voltage potential. The average voltage potential is a high-pass filtered version of the local (I/O VDD 36−I/O VSS 38)/2; its low frequency cutoff clears the low end of the resonance range and it also rejects the tracking of low-frequency disturbances that result from non-resonance behavior. The coupled instantaneous voltage potential feeds a feedback loop of the I/O interface 30 as charge is pumped in and out of the switched capacitors 32 and 34 that are coupled to the I/O power supply grid in an attempt to overcome I/O voltage variations, i.e., I/O power supply oscillations. The compensated high frequency cutoff ensures stable loop response while also clearing the high end of the resonance range.
FIG. 4 shows modeled circuit behavior associated with the I/O interface design shown in FIG. 3. In FIG. 4, fully charged capacitors 32 and 34 (of equal value in this implementation) are stacked in series 33 across the I/O power supply grid, i.e., in between I/O VDD 36 and I/O VSS 38. In this arrangement, the capacitors 32 and 34 serve as a voltage multiplier for the I/O power supply grid. The depleted voltage in each capacitor 32 and 34 is I/O VDD/n, where n is the number of capacitor stacks. Conversely, the stacked capacitors 32 and 34 store charge from the I/O power supply grid until the terminals across the capacitors 32 and 34 are at I/O VDD 36.
A capacitance amplification factor, G, represents the charge supplied to the I/O power supply grid by the switched capacitors 32 and 34 normalized to the charge furnished by regular decoupled capacitors given the same supply voltage variation. The amplification can be expressed as G=(k+n−1)/(k*n2), where n is the number of capacitor stacks and k is the voltage regulation tolerance. With each capacitor having a value C, the equivalent unstacked capacitance of C*n is reduced to C/n upon stacking with a total stack voltage of I/O VDD 34*n.
As shown in FIG. 4, when the instantaneous voltage potential falls below the average voltage potential, the capacitors 32 and 34 are switched to an arrangement in which discharging occurs, thereby providing charge to the I/O power supply grid. Alternatively, when the average voltage potential falls below the instantaneous voltage potential, the capacitors 32 and 34 are switched to an arrangement in which charging occurs, thereby drawing charge from the I/O power supply grid.
FIG. 5 shows the operation of the I/O interface 30 shown in FIG. 3 in conjunction with the discussion above with reference to FIG. 4. Specifically, FIG. 5 shows (1) a steady state when the average voltage potential is equal to the instantaneous voltage potential, (2) a discharging phase when the instantaneous voltage potential is less than the average voltage potential, and (3) a charging phase when the instantaneous voltage potential is greater than the average voltage potential. The high frequency and low frequency cutoffs are also shown for their respective phases.
While the method of using stacked capacitors has been demonstrated to be effective in minimizing the effect of parasitic inductance, space is at a premium in I/O interface design. Any design that obtains the same or better performance while reducing the required area on the I/O interface yields significant cost and design benefits.